ハイブリッド接合

セミナー概要 セミナーのテーマ ハイブリッド接合技術 ガラスパッケージング技術 Co-Packaged Optics (CPO)技術 こんな方におすすめです 半導体後工程に関する最新の研究動向を知りたい方 ECTC2025に参加できなかった方 ECTC2026への投稿を検討している方 ＜ECTC2025での発表を解説＞先端半導体パッケージング・実装技術の研究開発動向 ～最新の技術発表を、その特長・開発背景等を含めて解説～～ハイブリッド接合・ガラスパッケージ・Co-Packaged Optics・チップレット異種集積等～ ★好評につき今年で５回目の開催！◎後工程関連の最新技術を扱う国際会議「ECTC2025」での注目の発表をレビュー。◎最新の研究発表に関する動向調査・情報収集にお役立て下さい。 講師 東北大学 大学院工学研究科 機械機能創成専攻 准教授 福島誉史 氏【講師紹介】 2001年4月～2003年3月 株式会社ピーアイ技術研究所 技術顧問 2003年4月～2004年7月 東北大学 ベンチャービジネスラボラトリー 講師（中核的研究機関研究員） 2004年8月～2010年3月 東北大学 大学院工学研究科 バイオロボティクス専攻 助手／助教 2010年4月～2015年3月 東北大学 未来科学技術共同研究センター 准教授 2015年4月～2016年7月 東北大学 大学院工学研究科 バイオロボティクス専攻 准教授 2016年3月～2017年7月 米国UCLA, Electrical Engineering Department, Visiting Faculty 2023年7月～熊本大学 半導体・デジタル研究教育機構 クロスアポイントメント教授 兼任 ～現在に至る セミナー趣旨、ポイント 昨今、特に話題を集める半導体パッケージングですが、これに関連した数ある国際会議の中でも最も大きく最新の技術が発表されるのがECTC (Electronic Components and Technology Conference)です。 今回のセミナーでは、半導体パッケージングの最新動向を紹介し、2025年5月に終えたECTC2025の中からハイブリッド接合、ガラス基板・ガラスパッケージ、Co-Packaged Optics（CPO）、異種チップレット集積の関連技術などを中心にハイライトを行います。ECTC2025の総発表件数419件（ポスター167件含む）から95件の注目発表をピックアップして解説する予定です。 こんな方におすすめ ◎半導体後工程（半導体パッケージング、半導体実装技術）に関する最新の研究発表の内容を知りたい方◎今年オンサイトで行われたECTC2025に参加できなかった方◎2025年10月にECTC2026に投稿し2026年2月にfull paperを書く予定の方◎この分野の動向や見どころ、方向性に関心のある方 などを主対象といたします。 得られる知識 半導体パッケージング技術最大の国際会議ECTCについて、今回はECTC2025で発表された研究内容を多く取り上げ、関連する技術の背景や他の技術との比較も含めて、その特長や技術の進展について初心者でも分かりやすく説明します。 プログラム １．ECTCの紹介と最近の研究動向、および用語の説明 1.1 ECTCの発表件数の推移や国別／研究機関別投稿状況 1.2 チップレット集積と先端パッケージング技術の動向 1.3 ハイブリッド接合の概要２．ハイブリッド接合 54件 Session 1: Processing and Packaging Articles for 3D Integration ・Paper 4. A Novel 3D Heterogeneous Integration Using 2 µm Bond Pitch Die-to-Wafer Hybrid Cu Bonding and Wafer Reconstruction Process (Samsung Electronics) ・Paper 5. Enabling Chip-to-Wafer Hybrid Bonding Scaling to 1 µm Pitch With Optimal Power Delivery Using New Bond Via Architectures (Intel) ・Paper 7. Integration Solution for Thin D2W Hybrid Bonding for Yield and Reliability (Applied Materials) Session 3: Hybrid Bonding Materials and Processing for Advanced Packaging ・Paper 1. Morphological Microstructure Characterization and Optimization of Nanocrystalline Copper Deposition for Fine-Pitch Hybrid Bonding Cu/SiO2 at Low Temperature (STMicroelectronics/CEA-Leti) ・Paper 2. Wafer-to-Wafer Bonding With Ultralow Thermal Resistance and High Bonding Energy (Intel) ・Paper 3. Novel Polymer for Hybrid Bonding With Precise Tunable Crosslink Density (Resonac) ・Paper 4. Hybrid Bonding With Particle Accommodation Using Polymer Dielectric: Design, Process and Yield Study (IME/Toray) ・Paper 5. Characterization of Self-Nanoparticulated Cu-Cu Interconnection for Low-temperature Hybrid Bonding (Tohoku University/ Daicel) ・Paper 7. Effect of Grain Size on Cu-Cu Bonding Quality for Fine-Pitch Hybrid Bonding Application (National Yang Ming Chiao Tung University) Session 8: Novel Structures and Processes for Chip-toWafer Hybrid Bonding ・Paper 1. 2 µm Pitch Direct Die-to-Wafer Hybrid Bonding Using Surface Protection During Wafer Thinning and Die Singulation (imec) ・Paper 2. Innovative Cool-Stacking Technology for High Performance and Energy-Efficiency SoIC® (TSMC) ・Paper 3. Influences of Chip Shape on Scaling in Chip-on-Wafer Hybrid Bonding (Sony) ・Paper 4. Warpage Engineering in C2W Hybrid Bonding Using Inter-Die Gap Fill Dielectrics for 2.5D/3D Integration (IME) ・Paper 5. Direct Transfer Bonding Technology Enabling 50-nm Scale Accuracy for Die-to-Wafer 3D/Heterogeneous Integration (Tazmo/LINTEC/ULVAC/Tohoku University/Science of Tokyo) ・Paper 6. Hierarchical Multi-layer and Stacking Vias With Novel Structure by Transferable Cu/Polymer Hybrid Bonding for High Speed Digital Applications (ITRI/Brewer Science) ・Paper 7. Scalable Chip-to-Wafer Hybrid Bonding Processes for Fine-pitch (3 µm and 6 µm) Interconnections (IME/Applied Materials) Session 9: Co-Packaged Optics and Hybrid Bonding Innovations for HI ・Paper 4. Self-Formed Barrier Using Cu-Mn Alloy Seed Applied to a 400nm Pitch Wafer-to-Wafer Hybrid Bonding Technology (imec) ・Paper 5. SiCN CMP Integration for Hybrid Bonding Application (Applied Materials) ・Paper 6. Inter-Die Hybrid Cu/Diamond Microbump Bonding for 3D Heterogeneous Integration (Purdue University/University of Aveiro) ・Paper 7. First Demonstration of Superior Characteristics of Co-Co Bonding With Passivation Structure at Low Thermal Budget for Advanced Packaging and UltraFine Pitch Applications (National Yang Ming Chiao Tung University) Session 14: New Materials and Processes in Wafer-to-Wafer Hybrid Bonding ・Paper 1. Integration, Materials and Equipment Innovations to Enable 100 nm Pitch W2W Bonding for Memory-to-Logic and Logic-to-Logic 3D Stacking (Applied Materials/EVG) ・Paper 2. Advanced Memory Wafer-to-Wafer Bonding With Support of Recyclable Carrier Systems (Micron) ・Paper 3. Development of Wafer-Level Wet Atomic Layer Etching Process Platform for Cu Surface Topography Control in Hybrid Bonding Applications (Samsung Electronics) ・Paper 4. Development of a Novel WoWoW Process for 1/1.3-inch 50 Megapixel Three-Wafer-Stacked CMOS Image Sensor With DNN Circuits (Sony) ・Paper 5. Wafer-to-Wafer Hybrid Bonding Technology With 300nm Interconnect Pitch (imec) ・Paper 6. Electrical Performance of Hybrid Bonding With Sub-Micron Cu-Cu Bonding Contacts: Effects of Scaling, Microstructure, and Surface Morphology (Binghamton University/IBM) ・Paper 7. Selective Ru Deposition on Cu Bond Pads to Enable Low Thermal Budget Hybrid Bonding for HBM Applications. (IME) Session 16: Manufacturing and Thermal Management Reliability ・Paper 7. Enhanced Electromigration Reliability of Cu/SiO2 Hybrid Joints Fabricated by (111)-Oriented Nanotwinned Cu (National Yang Ming Chiao Tung University/ITRI) Session 19: Chiplet Integration and Advanced Thermal Solutions ・Paper 3. Mid-BEOL Heterogeneous Integration Through Sub-1 µm Pitch Hybrid Bonding &amp; Advanced Silicon Carrier Technologies for AI &amp; Compute Applications (Intel) Session 21: Meeting AI Challenges: Large Package Solution and Warpage Management for Advanced Packaging ・Paper 7. Innovative Silicon Die Thinning and Edge Protection of Chip-to-Wafer Hybrid Bonded Wafer for High-Density Multi-Chip Stacking (IME/Entegris) Session 22: Heterogeneous Integration Using Bridge and 3D Stacking ・Paper 1. Hybrid Bonding With Fluidic Self Alignment: Process Optimization and Electrical Test Vehicle Fabrication (Intel) ・Paper 3. Assessing Queue Time in D2W Hybrid Bonding Through Precise Bond Strength Measurements (Yokohama National University/Toray Engineering/DISCO/Tohoku University/University of Tsukuba) Session 32: Design, Materials, Metrology &amp; Standards for Next Generation Interconnections ・Paper 2. Are Voids Restricted to Cu-Cu bonding Interface? Truth Revealed by CEY Scanning Transmission X-ray Microscopy (Tohoku University/KEK) ・Paper 3. Ultra-Fast Cu/Polymer Hybrid Bonding With Electroless Passivation Layer for Cost-Effective High I/O Interconnection Stacking (National Yang Ming Chiao Tung University/TOK) ・Paper 6. A Study About Bonding Properties With Multilayer Porous Structures for Fine Pitch Interconnection (Mitsubishi Materials) Session 36: Modeling Driven Packaging and Process Advancements ・Paper 6. Simulation of Mechanical Cu Pad Expansion Mechanism and Measures to Increase Expansion (Sony) Session 37: Interactive Presentations 1 ・Paper 21. Thermal Characterization of HBMs Integrated via Hybrid Bonding (IME) ・Paper 24. Digital Design of Inter-Die Gap Fill Dielectric Film Processing for C2W Hybrid Bonding Using Finite Element Modelling (IME) ・Paper 25. Mitigation of Wafer-to-Wafer Bonding Distortions Through Accelerated Simulations and Measurements (imec) Session 39: Interactive Presentations 3 ・Paper 4. The Role of Surface Preparation and Bonding Parameters in Improving Hybrid Bonding Quality (Seoul National University of Science and Technology) ・Paper 6. Electrical Performance of 2-Platen CMP Process for Hybrid Bonding Application With Conventional / nt-Cu and Low Temperature of SixNy/SixOy Dielectrics (Intel/Applied Materials) ・Paper 10. Wet-Chemical Cu Cleaning for Fine-Pitch Hybrid Bonding (Yokohama National University/imec/Kurita Water Industries) ・Paper 13. A Mild Surface Activation Under Redox Gases Using Vacuum Ultraviolet Irradiation for Interconnection of Semiconductor Packaging (Ushio) ・Paper 15. A High Throughput Low-Temperature Copper-Copper Thermal Compression Bonding Scheme Using Tin Passivation (UCLA) ・Paper 16. Advanced Face-To-Back CoW 2.0 µm Pitch Cu-Cu Hybrid Bonding Process for Three Layer- Stacked 3D Heterogeneous Integration. (Sony) ・Paper 17. Process Approaches to Enable 200°C Hybrid Bonding With SiCN Bond Layer and 0.5 µm Pitch (Applied Materials/ EVG) ・Paper 18. High-Quality Cu µ-Joints by High-Throughput Contactless Hot-Isostatic-Pressure (HIP) Annealing for Chip-to-Wafer and Wafer-to-Wafer Hybrid Bonding (Tohoku University/Kobe Steel) ・Paper 22. Effect of Dimension on Thermal Expansion of Cu Pads in SiO2 Vias for 3D IC Fine-Pitch Hybrid Bonding (National Yang Ming Chiao Tung University) ・Paper 25. Process Development, Challenges, and Strategies for Void-Free Multi-Chip Stacking in Hybrid Bonding Application (IME) ・Paper 26. Ozone-Ethylene Radical Activation of SiCN/Cu Without Water Rinsing for Hybrid Bonding (Tohoku University/Meiden Nanoprocess Innovations) Session 40: Interactive Presentations ・Paper 10. Wafer-to-Wafer Bonding With Saddle-Shaped Wafers (imec/EVG) ・Paper 13. Bond Wave Analysis of SiCN for Fine Pitch Hybrid Bonding (Yokohama National University/Tokyo Electron/SK Hynix) ・Paper 14. Characterization of Interfacial Fracture Strength in Hybrid Bonded Wafers: A Novel Approach for High-Resolution Spatial Profiling (IBM/UCLA) Session 41: Student Interactive Presentations ・Paper 31. Reliable Bonding Strength Measurement of SiCN/SiCN Films by Four-point Bending Methodology (National Yang Ming Chiao Tung University/National Tsing Hua University) 3．ガラス関連技術 22件 Session 4: Large Package Manufacturing and Panel Level Processing ・Paper 6. Glass-Core Advanced Packaging Substrate Post-Dicing Die Strengths Comprehensive Comparisons for Different Singulation Methods - Dicing Induced SeWaRe Failures Re-Visited Ten Years Later (DISCO USA) ・Paper 7. Fundamental Transmission Performance Evaluation of Sub-2 Micron Fine-Wiring on Glass Core Substrate (DNP) Session 11: Emerging Trends: Towards High Speed, Secure, Reliable, and Sustainable Packaging ・Paper 2. Embedded Silicon Chip Capacitors in Glass Package for Vertical Power Delivery (CHIMES, SRC/Georgia Institute of Technology/Pennsylvania State University) Session 20: Novel Technologies for High Density RDL Interposers ・Paper 2. Panel Level Interposer by Using Glass Carrier for 2.5D Advance IC Package Application (ITRI/Applied Materials/FAVITE) Session 22: Heterogeneous Integration Using Bridge and 3D Stacking ・Paper 6. A Novel Thermal Isolation Method With Embedded ‘Glass Bridge’ Structures in Silicon-Based 2.5D Heterogeneous Integration Systems (Purdue University) Session 24: Advanced Characterization and Modeling of Next Generation Packaging Materials ・Paper 6. Physics-Based Modeling With Nanoindentation on the Mechanical Reliability of TGV Substrates Under Annealing Effects (ITRI/National Tsing Hua University/Applied Materials) Session 25: Advanced Substrate Technologies- Organic, Embedding and Glass ・Paper 1. Development of Glass Core Substrates for Long-Term Reliability Under Thermal Stress (DNP) ・Paper 5. Glass Core Substrate versus Organic Core Substrate (Unimicron) ・Paper 6. Development of Glass Core Build-Up Substate With TGV (Shinko) ・Paper 7. High-Aspect-Ratio, 6 µm-Diameter Through-Glass-Via Fabrication Into 100 µm-Thick ENA1 by Dry Laser Micro-Drilling Process (University of Tokyo/AGC) Session 26: Process Innovation in Through-Via and Solder Interconnection ・Paper 1. Deep Via and Trench Etching of Low CTE Glass Package Substrate Using SF6, NF3 and H2O Based NLD Plasma Process (ULVAC/Northeastern University) ・Paper 2. Development of Straight, Small-Diameter, High-Aspect Ratio Copper-Filled Through-Glass Vias (TGV) for High-Density 3D Interconnections (Purdue University/Taiwan Foresight) ・Paper 3. Metallization of Helium Tight and Thermo-Mechanically Reliable Through Glass Vias (TGV) by Conformal Pinched Via (CPV) Approach (Corning) Session 29: Advances in Additive Manufacturing, Wearable and Medical Technologies ・Paper 3. Direct Digital Manufacturing for Laser-Drilled Vias in Multilayer Glass Additively Manufactured Electronics (nScrypt/Sciperio) Session 33: Innovative Interconnects and Through Via Technology for 3D Packaging ・Paper 6. Dry Film Photo-Imageable Dielectric Enabling Glass Core Substrate TGV Filling and Build-Up (DuPont) Session 35: High-Performance Antenna and RF Design ・Paper 1. 3D Vertical Glass Stacking for 6G Communications - Interconnect Fabrication and Broadband Characterization (Georgia Institute of Technology/Pennsylvania State University) Session 36: Modeling Driven Packaging and Process Advancements ・Paper 2. Multi-Layer Sequential Fabrication and Mechanics-Based Model of Glass-Core Packages With Embedded Dies (Georgia Institute of Technology) Session 39: Interactive Presentations 3 ・Paper 3. Fabrication of D-band (140 GHz) Broadband Antenna Using Quartz Glass on Silicon Hybrid Bonded Wafer With Cavity (NGK/Fraunhofer IZM/Brandenburg University of Technology) Session 40: Interactive Presentations 4 ・Paper 21. Electrolytic Copper Plating Process for Glass Substrates (Uyemura) Session 41: Student Interactive Presentations ・Paper 4. 3D Coupled Line Inductors With Through-Glass Vias for Compact Passive Circuit Integration in Glass Packages (Gachon University/Korea Electronics Technology Institute) ・Paper 14. Organic and Hybrid Nanoscale Films for Low Loss Direct Glass-Copper Metallization (Georgia Institute of Technology) ・Paper 17. Chiplet Embedding in Glass-Core Package RDL (Georgia Institute of Technology)4．CPO関連技術 14件 Session 2: Co-Packaged Optics ・Paper 1. Heterogeneous Integration of Fiber-Based Co-Packaged Optics With EMIB Technology: Assembly, Performance, and Reliability (Intel) ・Paper 2. 6.4Tbps, 224Gbps/Lane Co-Packaged Optical Engines With Fine Pitch Through-Package Interconnects: Powering AI/ML and Next-Gen Data Centers (IME/Rain Tree Photonics) ・Paper 3. Flip-Chip Photonic-Electronic Integration Platform for Co-Packaged Optics Using a Glass Substrate With Vertically-Coupled Beam Expanding Lens (Sumitomo Electric Industries) ・Paper 4. Optical and Electrical Characterization of a Compact Universal Photonic Engine (TSMC) ・Paper 5. Large-Scale Glass Waveguide Circuit for Board-Level Optical Interconnects Between Faceplate and Co-Packaged Optical Transceivers (Corning/Fraunhofer IZM) ・Paper 6. All-SMF Arrays for Co-Packaged Optics: Optimizing Cost, Complexity, and Performance (NVIDIA) Session 7: High Performance Computing and Design Challenges and Solutions ・Paper 6. PM - Co-Packaged Optics (CPO) Technology Full Module Test Vehicle Demonstrations (IBM/IBM Tokyo) Session 9: Co-Packaged Optics and Hybrid Bonding Innovations for HI ・Paper 1. Demonstration of Co-Packaged Optics Assembly for Fiber-Based Optical Interconnect (Intel) ・Paper 2. Optical Multi-Chip Interconnect Bridge (OMIB™) Interposer Assembly Process to Enable High- Density Photonic Interconnects for High-Performance Computing Applications (Celestial AI) ・Paper 3. Advanced Glass Substrate Fabrication and Metallization Process Technology for Co-Packaged Optics (Corning) Session 15: Photonics Integration and Subsystems ・Paper 6. Stress, Thermal and Optical Performance (STOP) Analysis of Co-Packaged Optical Processor With FPGA-Memory-Optics-Power Integration (LightSpeed Photonics/IME) Session 32: Design, Materials, Metrology &amp; Standards for Next Generation Interconnections ・Paper 5. Study of High-Density Optical Redistribution Layer Enabling Advanced Chiplet Edge Bandwidth Density on Active Optical Package Substrate (AIST) Session 38: Interactive Presentations 2 ・Paper 26. Novel Optical Chiplet Structure Based on MCeP® (Shinko) ・Paper 27. Enabling Heterogeneous Integration of Optoelectronic Circuits via Die-to-Die Low- Temperature Bonding With Ultrathin dielectrics. (IME)5. その他の注目論文 5件 Session 1: Heterogeneous Chiplet Integration ・Paper 1. SoW-X: A Novel System-on-Wafer Technology for Next Generation AI Server Application (TSMC) Session 7: High Performance Computing and Design Challenges and Solutions ・Paper 2. Development of Embedded Multi Si Bridge Package in Panel Level Process for HPC/AI Applications (Samsung Electronics) Session 22: Heterogeneous Integration Using Bridge and 3D Stacking ・Paper 7. FOCoS-Bridge for Emerging Trends in High-Performance Computing (HPC) and Artificial Intelligence (AI) (ASE) Session 40: Interactive Presentations 4 ・Paper 19. Fabrication of Panel-Level Redistribution Interposer with 1.5/1.5 μm Multilayer Fine Wiring and Solutions to Issues of Miniaturization (Resonac) Session 32: Design, Materials, Metrology &amp; Standards for Next Generation Interconnections ・Paper 7. Massive Orthogonal Stacking Assembly of IC (MOSAIC) Cube With Inductive Coupling for Exascale Memory Applications (University of Tokyo/Tohoku University/EBARA/Yamaha Robotics Holdings)